I want to use my verilog source-code in third party component. it should be a bootloader
with microcontroller. bootloader should be read from hard disk. hard disk is not a microcontroller.
hard disk reads bootloader from disc.
bootloader is a file. hd
next bootloader is file2.hd. next bootloader is file3.hd.
I want that each bootloader should have counter & i want counter to increase as bootloader increase.
my bootloader is counter 6 bit(version 9.03). i want to increase my counter on each bootloader load.
eg 1. bootloader read bootloader from disc, counter = 0, 2nd bootloader read 2nd bootloader from disc, counter = 0, 3rd bootloader read 3rd bootloader from disc. counter
I want to increase counter by using LFSR-counter-generator
please give me solution. I want my bootloader to be file size less that 200kb(bootloader not complete).
Here’s a simple example for a 3-bit LFSR (I’ve used pseudo-code rather than actual Verilog; it shouldn’t be too hard to convert it):
bits 8 8 8
logic [3:0] x;
always @ (posedge clk) begin
if (rst) begin
x > 2;
You’ll need to add your counters to the appropriate places in this code, and put the code into a test bench, to get it working.
In a real-world design, you wouldn’t normally change the bits of the LFSR. It might need to be a register, but it would be initialized in your design.
If you had a design where the design had to stay “small” and a block of bytes was too big to fit into your block of memory, you’d have a smaller problem. You’d need to roll your own bootloader.
Imagine that you can have the second one for free.
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